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ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 8.0 V ? V PWR = V SUP ? 40 V, -40 ? C ? T A ? 135 ? C, unless otherwise noted. Typical
values noted reflect the approximate parameter means at T A = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
GATE DRIVE (CONTINUED)
Duty Cycle (44) , (45)
100% Duty Cycle Duration (44) , (45)
Maximum Programmable Deadtime (46)
t DC
t DC
t MAX
0.0
–
10.2
–
–
15
96
Unlimited
19.6
%
s
μs
OVER-CURRENT COMPARATOR
Over-current Protection Filter Time
Rise Time (OC_OUT)
t OC
t ROC
0.9
10
–
–
3.5
240
μs
ns
10% - 90%
C L = 100 pF
Fall Time (OC_OUT)
t FOC
10
–
200
ns
90% - 10%
C L = 100 pF
DESATURATION DETECTOR AND PHASE COMPARATOR
Phase Comparator Propagation Delay Time to 50% of V DD ; C L ?? 100 pF
ns
Rising Edge Delay
Falling Edge Delay
t R
t F
–
–
–
–
200
350
Phase Comparator Match (Prop Delay Mismatch of Three Phases)
t MATCH
–
–
100
ns
C L = 100 pF (44)
Desaturation and Phase Error Blanking Time (47)
(44)
Desaturation Filter Time (Filter Time is digital)
Fault Must be Present for This Time to Trigger
t BLANK
t FILT
4.7
640
7.1
937
9.1
1231
μs
ns
CURRENT SENSE AMPLIFIER
Output Settle Time to 99% (44) , (48)
t SETTLE
μs
RL = 1.0 k ? , C L = 500 pF, 0.3 V < V O < 4.8 V, Gain = 5 to 15
–
1.0
2.0
Notes
44. This parameter is guaranteed by design, not production tested.
45. As duty cycle approaches the limit of 100% or 0% there is a maximum and minimum which is not achievable due to deadtime,
propagation delays, switching times and charge time of the bootstrap capacitor (for the High Side FET). 0% is available by definition
(FET always OFF) and unlimited ON (100%) is possible as long as gate charge maintenance current is within the trickle charge pump
capacity.
46. A Minimum Deadtime of 0.0 can be set via an SPI command. When Deadtime is set via a DEADTIME command, a minimum of 1 clock
cycle duration and a maximum of 255 clock cycles is set using the internal time base clock as a reference. Commands exceeding this
value limits at this value.
47. Blanking time, t BLANK , is applied to all phases simultaneously when switching ON any output FET. This precludes false errors due to
system noise during the switching event.
48. Without considering any offsets such as input offset voltage, internal mismatch and assuming no tolerance error in external resistors.
33937A
Analog Integrated Circuit Device Data
14
Freescale Semiconductor
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